About Me

I am was a Ph.D. student at Georgia Tech, where I worked on the topics in Computer Architecture with Prof. Hyesoon Kim and other researchers. My research interests are in the interactions between microarchitecture, compilers, and operating systems to efficiently enable emerging architectures and technologies. I worked as a system programmer at a startup in Korea (2002-2005, 2007-2008) and also as an intern at AMD Research (2012)/Intel Labs (2013). I received my Ph.D. from Georgia Tech (2015) and my B.S. degree from Seoul National University (2007).


FPL-27 High Performance Binary Neural Networks on the Xeon+FPGA Platform
Duncan Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit Mishra, Debbie Marr, Suchit Subhaschandra, Philip H.W. Leong
Proc. of the 27th International Conference on Field-Programmable Logic and Applications (FPL), Ghent, Belgium, Sep 2017
[To Appear]

FPGA'17 Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Gee Hock Ong, Yeong Tat Liew, Srivatsan Krishnan, Duncan Moss, Suchit Subhaschandra, Guy Boudoukh
Proc. of the 25th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, California, Feb 2017 (Covered in the news by the Next Platform)

HPCA-23 GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
Lifeng Nai, Ramyad Hadidi, Jaewoong Sim, Hyojong Kim, Pranith Kumar, Hyesoon Kim
Proc. of the 23rd International Symposium on Higher Performance Computer Architecture (HPCA), Austin, TX, Feb 2017

FPT'16 Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC
Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit Mishra, Ganesh Venkatesh, Debbie Marr
Proc. of the 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, China, Dec 2016

FPL-26 Accelerating Recurrent Neural Networks in Analytics Servers: Comparison of FPGA, CPU, GPU, and ASIC
Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit Mishra, Srivatsan Krishnan, Debbie Marr
Proc. of the 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, Aug 2016

PACT-24 BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models
Joo Hwan Lee, Jaewoong Sim, Hyesoon Kim
Proc. of the 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), San Francisco, CA, Oct 2015 (Best Paper Award)
[PDF] [BibTex]

MICRO-47 Transparent Hardware Management of Stacked DRAM as Part of Memory
Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim
Proc. of the 47th International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec 2014
[PDF] [Slide] [Poster] [BibTex]

TOPPICKS'14 A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
IEEE Micro, Special Issue: Micro's Top Picks from 2013 Computer Architecture Conferences (MICRO TOP PICKS), May/June 2014
[Paper] [BibTex]

ISCA-40 Resilient Die-stacked DRAM Caches
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
Proc. of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013
One of the 12 computer architecture papers of 2013 selected as Top Picks by IEEE MICRO
[PDF] [Slide] [BibTex]

MICRO-45 A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi
Proc. of the 45th International Symposium on Microarchitecture (MICRO), Vancouver, BC, Canada, Dec 2012
[PDF] [Slide] [Poster] [BibTex]

ISCA-39 FLEXclusion: Balancing Cache Capacity and On-Chip Bandwidth via Flexible Exclusion
Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim
Proc. of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012
[PDF] [Slide] [BibTex]

PPoPP'12 A Performance Analysis Framework for Identifying Potential Benefits in GPGPU Applications
Jaewoong Sim, Aniruddha Dasgupta, Hyesoon Kim, Richard Vuduc
Proc. of the 17th International Symposium on Principles and Practice of Parallel Programming (PPoPP), New Orleans, LA, Feb 2012
[PDF] [Slide] [BibTex]


Multi-Level System Memory Having Near Memory Space Capable of Behaving as Near Memory Cache or Fast Addressable System Memory Depending on System State
Method and Apparatus for Implementing a Heterogeneous Memory Subsystem US20150278091
Predicting Outcomes for Memory Requests in a Cache Memory US20140143502
Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode US20140143505
Memory Scheduling for RAM Caches Based on Tag Caching US20140181384
Dirty Cacheline Duplication US20140173379
Bypassing a Cache when Handling Memory Requests US20140143493
Partitioning Caches for Sub-Entities in Computing Devices US20140173211
Bypassing Memory Requests to a Main Memory US20140164713